Solid state storage devices (for example, solid state drives) may be comprised of one or more packages of non-volatile memory dies, where each die is comprised of storage cells, where storage cells are organized into pages and pages are organized into blocks. Each storage cell can store one or more bits of information. A multi-level cell non-volatile memory cell for example, MLC NAND representing two bits of information is programmed with four threshold voltage levels, E, P1, P2, and P3.
A retention error occurs when the stored voltage level for a cell experiences leakage and transitions or migrates to a lower threshold level, such as from P3 to P2, P2 to P1, or P1 to E. Retention errors may also occur as a result of operations that introduce a voltage shift (higher or lower), such as a read or write disturbance. Error correction code techniques identify the location of the errors by calculating a syndrome and using the syndrome along with parity information to correct errors in bits determined to have errors.
There is a need in the art for improved techniques for determining the location of the data experiencing the errors to calculate the syndrome and use with the parity information to correct retention errors.